1. The Field of the Invention
The present invention relates to metal lines used for electrically connecting devices on an integrated circuit and more specifically to the formation of aluminum lines in which the void formation therein is suppressed.
2. The Relevant Technology
Integrated circuits are manufactured by an elaborate process in which a variety of different electronic devices are integrally formed on a semiconductor substrate such as a small silicon wafer. In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. The term semiconductor substrate is contemplated to include such structures as silicon-on-insulator and silicon-on-sapphire.
Conventional electronic devices include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices are formed on a single wafer. One of the final steps in the manufacture of integrated circuits is to form interconnect lines between a select number of the devices on the integrated circuit. In turn, the interconnect lines are connected to leads which can then be connected to other electrical systems. The interconnect lines in conjunction with the leads allow for an electrical current to be delivered to and from the electronic devices so that the integrated circuit can perform its intended function.
The interconnect lines generally comprise narrow lines of aluminum. Aluminum is typically used because it has a relatively low resistivity, good current-carrying density, superior adhesion to silicon dioxide, and is available in high purity. Each of these properties is desirable in interconnect lines since they result in a quicker and more efficient electronic circuit.
The computer industry is constantly under market demand to increase the speed at which integrated circuits operate and to decrease the size of integrated circuits. To accomplish this task, the electronic devices on a silicon wafer are continually being increased in number and decreased in size. In turn, the size of the interconnect lines must also be decreased.
As the interconnect lines get smaller, however, a phenomenon referred to as xe2x80x9cvoid formationxe2x80x9d has been found to occur more frequently. In general, void formation is a process in which minute voids formed within the aluminum line coalesce on the boundaries of the aluminum line. As a result of the coalescing of the voids, the aluminum line begins to narrow at a specific location. If the aluminum line gets sufficiently narrow, the line can burn out so as to cause an open in the line. The open prevents the integrated circuit from operating in a proper manner.
Void formation is generally caused by either electromigration or stress migration. Electromigration occurs as an electrical current flows through an aluminum line. When a voltage is applied across an aluminum line, electrons begin to flow through the line. These electrons impart energy to the aluminum atoms sufficient to eject an aluminum atom from its lattice site. As the aluminum atom become mobile, it leaves behind a vacancy. In turn, the vacancy is also mobile since it can be filled by another aluminum atom which then opens a new vacancy. In the phenomenon of electromigration, the vacancies formed throughout the aluminum line tend to coalesce at the grain boundaries of the aluminum line, thereby forming voids that narrow the interconnect line as discussed above. Once the interconnect line is narrowed, the current density passing through that portion of the line is increased. As a result, the increased current density accelerates the process of electromigration, thereby continually narrowing the line until the line fails.
It is also thought that void formation occurs as a result of stress migration inherent in aluminum line deposition. The deposition of the aluminum lines is usually done at an elevated temperature. As the aluminum cools, the aluminum begins to contract. An insulation layer positioned under the aluminum layer, typically silicon dioxide, also contracts. The aluminum and the silicon dioxide have different coefficients of thermal expansion and contraction such that the two materials contract at different rates. This contraction sets an internal stress within the aluminum line. The same phenomenon can also occur when a subsequent layer is formed over the top of the aluminum line. It is theorized that the energy resulting from the induced stress within the aluminum causes displacement of the aluminum atoms and coalescence of the resulting vacancies.
FIG. 1 illustrates the problem of voids in exposed interconnect lines that are composed of aluminum. A semiconductor structure 10 is seen in FIG. 1 that includes a silicon substrate 12, a insulating layer 14, and interconnect lines 27 and 29 on insulating layer 14. Silicon substrate 12 has an active area therein to which a contact is made by a plug 15 having a liner 13 thereover. Plug 15 is preferably composed of aluminum or tungsten, and liner 13 is preferably composed of titanium nitride or a combination and titanium and titanium nitride. Upon insulating layer 14 is layer 17 composed of titanium and layer 19 composed of titanium aluminide. A layer 20 is composed aluminum and a layer 22 is composed of titanium nitride. Interconnect lines 27 and 29 have been patterned as illustrated.
A void 21 is seen in aluminum layer 20. The occurrence of a high mechanical stress field in aluminum layer 20 initiates the formation of void 21. Consequently, there is a coalescing of vacancies in the aluminum grain in the high mechanical stress field. Temperatures common in fabrication processes also aggregate the voiding problem. If a voiding problem occurs due to stress migration, electromigration effects will be accelerated in the void location due to the higher current density under operating conditions.
In one attempt to eliminate void formation, the aluminum is mixed with another metal to form an aluminum alloy. For example, copper has been added to aluminum In turn, the copper appears to increase the energy required to cause the voids to form in the line. This remedy, however, is only partial since void formation still occurs over time, especially as the size of the aluminum line decreases.
What is needed in the art is an effective method and structure to prevent void formation due to stress migration, electromigration, and related problems.
The present invention includes an inventive method of forming a conductively clad interconnect line structure. The interconnect line structure is fabricated by forming a first refractory metal layer upon a electrically insulative substrate. A metal layer is then formed upon the first refractory metal layer. Co-planar opposing sides are formed on both the first refractory metal layer and the metal layer, and a second refractory metal layer is conformally formed upon both the metal layer and the first refractory metal layer. Then, spacers are formed from the second refractory metal layer on the co-planar opposing sides on the first refractory metal layer, where the second refractory metal layer covers the metal layer.
The present inventive also includes a conductively clad interconnect line structure that includes a first refractory metal layer upon a electrically insulative substrate, a metal layer upon the first refractory metal layer, where there are co-planar opposing sides on both the first refractory metal layer and the metal layer, and a spacer, composed of a second refractory metal layer, on each of the co-planar opposing sides on the first refractory metal layer, where the second refractory metal layer covers the metal layer.
The present invention provides an improved interconnect line for connection to an electronic device within an integrated circuit. The interconnect line is an electrically conductive layer, such as an aluminum layer, positioned on the integrated circuit and having an exterior surface defined by a bottom surface, a top surface, and opposing side surfaces. A discrete bottom metal layer is secured to and substantially covers the bottom surface of the electrically conductive layer. A discrete top metal layer is secured to and substantially covers the top surface of the electrically conductive layer. Finally, discrete metal sidewall spacers individually attach to and substantially cover each of the opposing side surfaces of the electrically conductive layer. In this embodiment, the electrically conductive layer is substantially encased by the bottom metal layer, top metal layer, and sidewall spacers. In a preferred embodiment, the bottom metal layer, top metal layer, and sidewall spacers are made from a refractory metal or nitrides thereof, preferably titanium or a titanium compound such as a nitride of titanium. By encasing the electrically conductive layer within such metals, or metal compounds, the effect of void formation is significantly reduced. A refractory metal for purposes of the invention described herein includes chromium, cobalt, molybdenum, platinum, tantalum, titanium, tungsten, zirconium, or combinations thereof.
The present invention also discloses a method for forming an inventive interconnect line for connection to an electronic device within an integrated circuit. Such an interconnect line is formed by initially depositing a first refractory metal layer on an integrated circuit formed on a semiconductor substrate. Next, an electrically conductive layer is deposited over the first refractory metal layer. A second refractory metal layer is then deposited over the electrically conductive layer.
Photolithography, which can be aided by an antireflective coating that is formed on the interconnect line, and etching are then used to further define the interconnect line. The etching removes portions of the first refractory metal layer, the electrically conductive layer, and the second refractory metal layer so as to form a narrow interconnect line having overlying portions of the first refractory metal layer, the electrically conductive layer, and second refractory metal layer. The interconnect line is in part defined by having opposing side surfaces where the electrically conductive layer is openly exposed.
Next, a third refractory metal layer is deposited over the semiconductor substrate to cover the interconnect line. A portion of the third refractory metal layer covers the side surfaces of the interconnect line.
Finally, anisotropic etching is used to remove the third refractory metal layer not covering the side surface of the interconnect line. As a result, the electrically conductive layer is encased by the first refractory metal layer, second refractory metal layer, and third refractory metal layer. To provide improved contact between the various metal layers, the interconnect line is then annealed at a temperature in a range from about 400xc2x0 C. to about 450xc2x0 C.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.